The Verillog® Hardware Description Language
Donald E. Thomas, Philip R. Moorby (auth.)xv From the Old to the New xvii Acknowledgments xxi 1 Verilog – A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 11 Behavioral Modeling of Combinational Circuits Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 14 Procedural Modeling of Clocked Sequential Circuits Modeling Finite State Machines 15 Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment ("
عام:
2002
الإصدار:
5
الناشر:
Springer US
اللغة:
english
الصفحات:
382
ISBN 10:
1402070896
ISBN 13:
9781402070891
ملف:
PDF, 7.95 MB
IPFS:
,
english, 2002